1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a dual damascene interconnecting line structure.
2. Description of the Related Art
As the density of components in integrated circuits increases, the highly conductive components of an integrated circuit must be extremely small to provide enough space for the other components. Meanwhile, back end of line (BEOL) processes integrate an increasing number of dual-damascene interconnect techniques to meet the stringent requirements of state of the art metal interconnect processes. However, the RC delay associated with metal interconnect is detrimental to the circuit performance. In order to reduce circuit capacitance, low-k dielectric materials are used and new conductive materials, multi-level structures and patterning techniques are being investigated.
Although conventional conductive components perform adequately for many applications, highly conductive components are beginning to limit the performance of extremely high density integrated circuits with very small components because the resistance per unit length of long, narrow conductive lines is undesirably high. Aluminum is desirable for short or wide conductive features, but it is too resistive for use in long, narrow conductive components. Tungsten is also used for conductive components, but it is difficult to fill small voids in dielectric layers with tungsten.
Generally, copper is more conductive than aluminum, but the resistance per unit length of copper conductive components may be too high for long, narrow conductive lines because copper loses an electron to the surrounding silicon and silicon oxide layers. Additionally, it is difficult to dry-etch a copper line due to the low vapor pressure of by-products during a dry etching process. Moreover, copper lines are particularly subject to corrosion such that it is difficult to use a copper line as a metal line in a semiconductor device. Typically, copper lines have lower resistance than other existing metal lines and also have excellent electro-migration properties.
Under the limitations mentioned above, the conventional process of fabricating a dual-damascene interconnecting line structure is more complex when two steps of lithography and etching are used. Additionally, between the steps of lithography and etching, there is a residual photoresist problem resulting in lower yield.
FIGS. 1A to 1E are cross-sections illustrating conventional methods of forming a dual damascene interconnecting line structure in a semiconductor device. Referring now to FIG. 1A, a first conductive layer 11 is formed on a semiconductor substrate 10, and then a first interlayer dielectric layer 12 is formed on the first conductive layer 11.
Referring to FIG. 1B, a first photoresist layer 15 having a via contact hole pattern is subsequently formed on the first interlayer dielectric layer 12. The first interlayer dielectric layer 12 is etched using the first photoresist layer 15 as a mask, thereby forming a via contact hole 16 exposing the first conductive layer 11.
Referring to FIG. 1C, a second photoresist layer 17 having an interconnect trench pattern is formed on a second interlayer dielectric layer 14. The second interlayer dielectric layer 14 is etched using the second photoresist layer 17 as a mask, thereby forming an interconnect trench 18 in the second interlayer dielectric layer 14. Thus, a dual-damascene opening structure 19 is achieved.
Referring to FIG. 1D, a second conductive layer 20 is formed on the second interlayer dielectric layer 14 and fills the interconnect trench 18 and the dual-damascene opening structure 19.
Referring to FIG. 1D, the second conductive layer 20 above the second interlayer dielectric layer 14 is removed to construct a dual damascene interconnecting line structure 21 with a plurality of contact vias and a damascene interconnecting line structure.
U.S. Pat. No. 6,498,092 discloses three possible options available for the formation of dual damascene structures: via-first, trench-first and a self-aligned process (also called buried-via). These three methods all require an etch stop layer with high dielectric constant, due to this, parasitic capacitance in the interlayer insulation layers is increased, thereby increasing RC delay during the operation of a semiconductor device.
U.S. Pat. No. 6,271,593 discloses a method and substrate structure for fabricating highly conductive components on microelectronic devices. However, a dielectric stratum having a high dielectric constant is used between the interlayer insulation layers, due to this; parasitic capacitance in the interlayer insulation layers is increased, thereby increasing RC delay during the operation of a semiconductor device.